CMOS logic circuit
US4816702A · kind A · utility
8Cited by
4References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1987 |
| Grant date | Mar 28, 1989 |
| Priority date | — |
| Expiry date | Dec 9, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0372
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS logic circuit for sampling data coming from TTL logic circuits under frequency control by a system's clock intrinsically faster than prior art similar circuits is obtained by combining a TTL/CMOS compatibility interface inverting stage with a first stage of the sampling circuit (master or latch stage). The circuit of the invention permits elimination of two inverters and therefore reduction of data transfer delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.