Sense amplifier with improved bitline precharging for dynamic random access memory
US4816706A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 1987 |
| Grant date | Mar 28, 1989 |
| Priority date | — |
| Expiry date | Sep 10, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel sense amplifier and decoupling device structure for integrated circuit memories wherein an embodiment of a cross-coupled sense amplifier includes two PMOS devices, the gates of which devices are grounded and clamp the downward voltage swing of the memory bitlines to the absolute value of the threshold voltage (VTP) of the grounded-gate PMOS devices in the sense amplifier. This limited voltage swing does not affect charge storage of storage capacitors because the absolute value of the threshold voltage (VT) of the cell transfer gate device is larger. Precharging the bitlines is achieved by equalizing the two bitlines, each charged to VDD and .vertline.VTP.vertline., respectively. One node of the sense amplifier retains a full VDD swing and is conveniently connected to the DATA bus. The sense amplifier bitline swing is limited to a swing of VDD-.vertline.VTP.vertline. and saves power without adversely affecting charge storage and the precharging level ##EQU1## and improves the signal development time during sensing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.