High density vertical trench transistor and capacitor memory cell structure and fabrication method therefor

US4816884A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Wei Hwang · Armonk, US
• Nicky C. Lu · Yorktown Heights, US

Key dates

• Filing date: Jul 20, 1987
• Grant date: Mar 28, 1989
• Expiry date: Jul 20, 2007

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/665

Abstract

A semiconductor memory cell structure incorporating a vertical access transistor over a trench storage capacitor including a semiconductor wafer having a semiconductor substrate and an epitaxial layer disposed thereon. A relatively deep polysilicon filled trench is disposed in the epitaxial layer and substrate structure, the deep trench having a composite oxide/nitride insulation layer over its vertical and horizontal surfaces to provide a storage capacitor insulator. A relatively shallow trench is disposed in the epitaxial layer over the deep trench region, the shallow trench having an oxide insulation layer on its vertical and horizontal surfaces thereof. A neck structure of epitaxial polysilicon material extends from the top surface of the polysilicon filled deep trench to the bottom surface of the shallow trench. Impurities are disposed in the epitaxial layer on either side of the shallow trench to form semiconductor device drain junctions and polysilicon material is disposed in the shallow trench and over the epitaxial layer to form semiconductor device transfer gate and wordline regions respectively.