Method for identification of parasitic transistor devices in an integrated structure
US4817012A · kind A · utility
28Cited by
2References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 25, 1986 |
| Grant date | Mar 28, 1989 |
| Priority date | — |
| Expiry date | Apr 25, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In order to identify parasitic transistors in bipolar integrated circuit structures, files relating to the parameters of the simulated circuit are established. These files are then manipulated to establish the operating parameters of the simulated circuit. These operating parameters are then examined to identify the conditions that lead to circuit degradation due to parasitic transistors. The structure in the integrated circuit that result in the parasitic transistors are then highlighted on the circuit display in order to facilitate appropriate design changes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.