Phase comparator for extending capture range
US4819081A · kind A · utility
47Cited by
9References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 3, 1987 |
| Grant date | Apr 4, 1989 |
| Priority date | — |
| Expiry date | Sep 3, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1072
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An extended range logic circuit is activated to decrease the settling time and prevent slip, when phase difference of two signals being compared by a phase comparator reaches a slip point. The circuit provides error correction signals to compensate for the phase correction at a much faster rate when the phase error reaches a predetermined point, which is proximate to the slip point. However, the extended capture range circuit in only active during the lock acquisition. After lock is achieved the extended capture range logic is disabled, to provide better jitter performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.