Roger Van Brunt
21Patents
18h-index
9Co-inventors
74Inventor score
Filing activity: Sep 3, 1987 → Sep 20, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5384808A | Method and apparatus for transmitting NRZ data signals across an isolation barrier disposed in an interface between adjacent devices on a bus | Electricity | 190 | Expired |
| US5579486A | Communication node with a first bus configuration for arbitration and a second bus configuration for data transfer | Physics | 99 | Expired |
| US5559967A | Method and apparatus for a dynamic, multi-speed bus architecture in which an exchange of speed messages occurs independent of the data signal transfers | Electricity | 83 | Expired |
| US5606268A | Differential to single-ended CMOS converter | Electricity | 73 | Expired |
| US5467464A | Adaptive clock skew and duty cycle compensation for a serial data bus | Electricity | 71 | Expired |
| US5418478A | CMOS differential twisted-pair driver | Electricity | 57 | Expired |
| US7773965B1 | Calibrated quadrature very low intermediate frequency receiver | Electricity | 55 | Active |
| US5592510A | Common mode early voltage compensation subcircuit for current driver | Electricity | 50 | Expired |
| US5485488A | Circuit and method for twisted pair current source driver | Electricity | 48 | Expired |
| US4819081A | Phase comparator for extending capture range | Electricity | 47 | Expired |
| US5412698A | Adaptive data separator | Electricity | 44 | Expired |
| US5493657A | High speed dominant mode bus for differential signals | Electricity | 33 | Expired |
| US5412697A | Delay line separator for data bus | Physics | 30 | Expired |
| US5384769A | Method and apparatus for a bus transceiver incorporating a high speed binary data transfer mode with a ternary control transfer mode having a full duplex, dominant logic transmission scheme | Electricity | 26 | Expired |
| US5778204A | High-speed dominant mode bus for differential signals | Electricity | 23 | Expired |
| US5619541A | Delay line separator for data bus | Physics | 23 | Expired |
| US5485458A | Bus interconnect circuit including port control logic for a multiple node communication network | Physics | 22 | Expired |
| US5424657A | Method and apparatus for implementing a common mode level shift in a bus transceiver incorporating a high speed binary data transfer mode with a ternary control transfer mode | Electricity | 19 | Expired |
| US5504458A | CMOS class AB amplifier for driving capacitive and resistive loads | Electricity | 17 | Expired |
| US9838026B2 | Apparatus and methods for fractional-N phase-locked loops with multi-phase oscillators | Electricity | 13 | Active |
| US8664991B1 | Apparatus and methods for phase-locked loops | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.