Self-aligned metallization for semiconductor device and process using selectively deposited tungsten
US4822749A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 1987 |
| Grant date | Apr 18, 1989 |
| Priority date | — |
| Expiry date | Aug 27, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/903
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A self-aligned metallization for an MOS device is described in which a first layer of tungsten is selectively deposited on the exposed silicon surfaces of the device including at least the source, drain and gate regions of the device, a layer of material providing nucleation sites for tungsten is selectively formed across insulating oxide regions of the device, and a second tungsten layer is selectively deposited on the nucleating layer and the exposed first tungsten layer to provide interconnection across the oxide regions. In addition to having a low electrical resistivity, such a metallization enables relaxed mask alignment and etching tolerance requirements, and is therefore useful in VLSI circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.