MOS floating gate memory cell containing tunneling diffusion region in contact with drain and extending under edges of field oxide

US4822750A · kind A · utility

Assignee

• Seeq Technology, Incorporated · US

Inventors

• Gust Perlegos · Merced, US
• Tsung-Ching Wu · Saratoga, US

Key dates

• Filing date: Jul 16, 1987
• Grant date: Apr 18, 1989
• Expiry date: Jul 16, 2007

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

A two device floating gate MOS nonvolatile memory cell is disclosed including a floating gate memory device coupled to a select device wherein a thin tunnel dielectric region of insulation material between the substrate and floating gate of the memory device is located in an area above the channel of the memory device in the substrate and wherein an implanted region in the substrate to facilitate the tunneling of carriers in and out of the floating gate extends appreciably underneath the edges of the field oxide regions forming the periphery of the sides of the channel of the memory device. A select device is located in series with the memory device. A process for fabricating this memory cell is also disclosed wherein the doped tunnelling region in the substrate is defined and implanted prior to definition of the field regions.