High voltage lateral MOS structure with depleted top gate region
US4823173A · kind A · utility
28Cited by
7References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 7, 1986 |
| Grant date | Apr 18, 1989 |
| Priority date | — |
| Expiry date | Jan 7, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/615
Abstract
The present invention provides an improved lateral drift region for both bipolar and MOS devices where improved breakdown voltage and low ON resistance are desired. A top gate of the same conductivity type as the device region with which it is associated is provided along the surface of the substrate and overlying the lateral drift region. In an MOS device, the extremity of the lateral drift region curves up to the substrate surface beyond the extremity of the top gate to thereby provide contact between the JFET channel and the MOS channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.