Semiconductor resin package structure
US4825284A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1986 |
| Grant date | Apr 25, 1989 |
| Priority date | — |
| Expiry date | Dec 10, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor resin package structure formed according to the flip-chip connection method and permitting to cool the rear surface of semiconductor chips, comprising semiconductor chip and carrier substrate which is soldered on one surface thereof to electrodes of the semiconductor chip according to the flip-chip connection method, the gap between the semiconductor chip and the carrier substrate being filled with resin having a thermal expansion coefficient, which is approximately equal to that of used solder, the electrodes of the semiconductor chip being electrically connected with terminals on the other surface of the carrier substrate through the soldered portions and a through-hole conductor disposed on the carrier substrate, the thermal expansion coefficient of the carrier substrate being approximately equal to that of a multi-layer substrate, with which the substrate is connected by soldering with the terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.