Process and circuit arrangement for addressing the memories of a plurality of data processing units in a multiple line system
US4829420A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 29, 1987 |
| Grant date | May 9, 1989 |
| Priority date | — |
| Expiry date | Jun 29, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0692
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A process and a circuit arrangement for the automatic direct addressing of any desired memory location in the memories of a plurality of data processing units interconnected through a common bus by use of a single-step addressing technique is disclosed. The size of the memories used in the various processing units may be different. Addresses may be internally stored in the memories according to one of two addressing schemes. In a data processing unit initiating a data transmission connection, the external memory address of the desired memory location to be addressed is generated from an internally stored address and is transmitted to the bus system. This external address is received in each data processing unit, which performs an address calculation to determine whether the specified external address is within its volume or range of addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.