High density memory cell structure having a vertical trench transistor self-aligned with a vertical trench capacitor and fabrication methods therefor

US4833516A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Wei Hwang · Armonk, US
• Nicky C. Lu · Yorktown Heights, US

Key dates

• Filing date: Aug 3, 1987
• Grant date: May 23, 1989
• Expiry date: Aug 3, 2007

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/63

Abstract

A new high density vertical trench transistor and trench capacitor DRAM (dynamic-random-access memory) cell is described incorporating a wafer with a semiconductor substrate and an epitaxial layer thereon including a vertical transistor disposed in a shallow trench stacked above and self-aligned with a capacitor in a deep trench. The stacked vertical transistor 14 has a channel partly on the horizontal surface and partly along the shallow trench sidewalls. The drain of the access transistor is a lightly-doped drain structure connected to a bitline element. The source of the transistor, located at the bottom of the transistor trench and on top of the center of the trench capacitor, is self-aligned and connected to polysilicon contained inside the trench capacitor. Three sidewalls of the access transistor are surrounded by thick oxide isolation and the remaining one side is connected to drain and bitline contacts. The memory cell is located inside an n-well and uses the n-well and heavily-doped substrate as the capacitor counter-electrode plate. The cell storage node is the polysilicon inside the trench capacitor and include steps for growing epitaxial layers wherein an opening is le…