Hierarchical priority branch handling for parallel execution in a parallel processor
US4833599A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 1987 |
| Grant date | May 23, 1989 |
| Priority date | — |
| Expiry date | Apr 20, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a parallel data processing system having a plurality of separately operating arithmetic processing units, a method and apparatus allows a plurality of branch instructions to be operated upon in a single machine cycle. The branch instructions have associated therewith a hierarchical priority system and the method and apparatus determine which branch, if any, should be taken. In particular, the method and apparatus simultaneously determine, during the parallel execution of the branch instructions, whether any branch test condition associated with a branch instruction is true, and independently, the target address for each branch instruction and a fall-through instruction address if a branch instruction is not taken.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.