Inventor · Portland, OR, US

Robert P. Colwell

40Patents
26h-index
24Co-inventors
81Inventor score

Filing activity: Apr 20, 1987 → Mar 12, 1999

Most-cited inventions

PatentTitleAreaCited byStatus
US4833599A Hierarchical priority branch handling for parallel execution in a parallel processor Physics 218 Expired
US5721855A Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer Physics 212 Expired
US5179680A Instruction storage and cache miss recovery in a high speed multiprocessing parallel processing apparatus Physics 117 Expired
US5057837A Instruction storage method with a compressed format using a mask word Physics 111 Expired
US4920477A Virtual address table look aside buffer miss recovery method and apparatus Physics 108 Expired
US5778245A Method and apparatus for dynamic allocation of multiple buffers in a processor Physics 86 Expired
US5627985A Speculative and committed resource files in an out-of-order processor Physics 86 Expired
US6349380B1 Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessor Physics 75 Expired
US6047369A Flag renaming and flag masks within register alias table Physics 66 Expired
US6079014A Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state Physics 59 Expired
US5499352A Floating point register alias table FXCH and retirement floating point register array Emerging Cross-Sectional Technologies 58 Expired
US5584038A Entry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversed Physics 58 Expired
US5446912A Partial width stalls within register alias table Physics 55 Expired
US5452426A Coordinating speculative and committed state register source data and immediate source data in a processor Physics 51 Expired
US5687338A Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor Physics 49 Expired
US5574942A Hybrid execution unit for complex microprocessor Physics 48 Expired
US5471633A Idiom recognizer within a register alias table Physics 45 Expired
US5561814A Methods and apparatus for determining memory operating characteristics for given memory locations via assigned address ranges Physics 44 Expired
US5546597A Ready selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction execution Physics 43 Expired
US5729728A Method and apparatus for predicting, clearing and redirecting unpredicted changes in instruction flow in a microprocessor Physics 40 Expired
US5307506A High bandwidth multiple computer bus apparatus Physics 39 Expired
US5809271A Method and apparatus for changing flow of control in a processor Physics 37 Expired
US5613132A Integer and floating point register alias table within processor device Physics 35 Expired
US5564056A Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming Physics 34 Expired
US5524262A Apparatus and method for renaming registers in a processor and resolving data dependencies thereof Physics 33 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.