Semiconductor memory device including programmable mode selection circuitry
US4833650A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 1987 |
| Grant date | May 23, 1989 |
| Priority date | — |
| Expiry date | Apr 2, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a plurality of operation mode control circuits provided on a memory chip of the device for respectively executing a corresponding plurality of writing/reading operation modes including at least a static column mode, a high speed page mode and a nibble mode, and a plurality of operation mode selection circuits provided on the memory chip, each of the operation mode selection circuits having a fuse element and a bonding pad for selecting one of the plurality of the operation mode control circuits when the fuse element is cut off or the bonding pad is selectively wired, so that various functions can be selectively effected on the same chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.