Semiconductor memory device performing multi-bit Serial operation
US4835743A · kind A · utility
2Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 3, 1987 |
| Grant date | May 30, 1989 |
| Priority date | — |
| Expiry date | Sep 3, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1033
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory device capable of nibble mode operation, the time period required from the time when CAS signal falls to the time when a data output buffer activating signal rises is made different at the time of a normal mode and at the time of a nibble mode, so that the time period required for reading out data in the nibble mode is reduced as compared with a conventional device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.