Package structure for semiconductor device
US4839713A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 1988 |
| Grant date | Jun 13, 1989 |
| Priority date | — |
| Expiry date | Feb 17, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01082
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package structure comprising a metallic cap having a bottom wall to which the bottom surface of the semiconductor chip is electrically and mechanically connected, a side wall extending from said bottom wall and surrounding the semiconductor chip, and a flange extending outwardly from said side wall substantially parallel to said bottom wall, said flange supporting the lead conductors thereon through an electrically insulating material. The electrical connection means is disposed between the metallic cap flange and the lead conductor for establishing an electrical connection therebetween. The electrical connection means may comprise an electrically conductive projection formed on the flange of the metal cap, extending through a notch in the insulating material and electrically connected to the lead conductor. The electrical connection means may be an electrically conductive bonding material filled within a cavity defined by an opening in the flange of the metal cap, a through hole in the insulating material and a connecting pad of the lead conductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.