Simultaneous multiple level interconnection process
US4840923A · kind A · utility
87Cited by
14References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 19, 1988 |
| Grant date | Jun 20, 1989 |
| Priority date | — |
| Expiry date | Oct 19, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/164
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system of establishing a conductive via path between spaced interlevel conductors. Successive layers of metallization separated by a dielectric are built. The vias are opened in one step to eliminate interlevel mashing. The system employs annular pads at locations where contact may be established to another wiring level. The vias are self-aligned and taper from top metal to first level contact. The system is applicable both chip-wise and carrier-wise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.