Semiconductor memory device
US4841481A · kind A · utility
28Cited by
1References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 28, 1988 |
| Grant date | Jun 20, 1989 |
| Priority date | — |
| Expiry date | Jul 28, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
Abstract
An SRAM including a memory cell having a high-resistance load element. The load element is formed from a polysilicon film, and an impurity is introduced into a least a part of the polysilicon film for the purpose of increasing the threshold voltage of a parasitic MISFET formed using the load element as its channel region. Alternatively, the deposition of the polysilicon film is carried out at a relatively high temperature, thereby preventing any increase in the current flowing through the load element, and thus reducing the power dissipation in the SRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.