Method of selective via-hole and heat sink plating using a metal mask
US4842699A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 1988 |
| Grant date | Jun 27, 1989 |
| Priority date | — |
| Expiry date | May 10, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for simultaneous selective plating of viaholes and heat sinks associated with a semiconductor wafer using a metal mask and comprising the steps of: PA1 (a) coating a first side of the wafer with an insulating layer to prevent electroplating on this first side; PA1 (b) patterning on a second side of the wafer, opposite to the first side, a metal mask for defining the areas where plating should not occur; PA1 (c) forming via-holes through said wafer; PA1 (d) depositing a thin conductive film to coat the bottom and walls of the via-holes as well as areas of the second side of the wafer not covered by the metal mask; and PA1 (e) electrolytically plating the resulting wafer while ultrasonically agitating the electrolyte if necessary to ensure sufficient electrolyte transport into the via-holes for uniform plating.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.