Microprocessor for retrying data transfer
US4845614A · kind A · utility
28Cited by
7References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 10, 1987 |
| Grant date | Jul 4, 1989 |
| Priority date | — |
| Expiry date | Aug 10, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/141
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor and a peripheral equipment communicate data through a bus. If an error occurs during communication, the microprocessor starts the next bus cycle and commands retry of the data communication. If a predetermined number of times of retry fail, and if an address signal corresponds to an unmounted area of an address space, wherein the unmounted area is an area of the address space not occupied by peripheral equipment including an I/O device, the microprocessor inhibits the retry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.