Makoto Hanawa
35Patents
16h-index
42Co-inventors
81Inventor score
Filing activity: Dec 23, 1985 → Sep 27, 2005
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5375215A | Multiprocessor system having shared memory divided into a plurality of banks with access queues corresponding to each bank | Physics | 51 | Expired |
| US5386394A | Semiconductor memory device for performing parallel operations on hierarchical data lines | Physics | 32 | Expired |
| US4845614A | Microprocessor for retrying data transfer | Physics | 28 | Expired |
| US4745302A | Asynchronous signal synchronizing circuit | Electricity | 28 | Expired |
| US5269007A | RISC system capable of simultaneously executing data interlocked shift and arithmetic/logic instructions in one clock cycle by bypassing register | Physics | 25 | Expired |
| US5572151A | Pass transistor type selector circuit and digital logic circuit | Electricity | 24 | Expired |
| US5301285A | Data processor having two instruction registers connected in cascade and two instruction decoders | Physics | 22 | Expired |
| US5253197A | Semiconductor associative memory device with current sensing | Emerging Cross-Sectional Technologies | 20 | Expired |
| US4989140A | Single chip pipeline data processor using instruction and operand cache memories for parallel operation of instruction control and executions unit | Physics | 19 | Expired |
| US5381531A | Data processor for selective simultaneous execution of a delay slot instruction and a second subsequent instruction the pair following a conditional branch instruction | Physics | 19 | Expired |
| US5125095A | System using microprocessor address lines for coprocessor selection within a multi-coprocessor apparatus | Physics | 18 | Expired |
| US5740401A | Multiprocessor system having a processor invalidating operand cache when lock-accessing | Physics | 18 | Expired |
| US6282505A | Multi-port memory and a data processor accessing the same | Physics | 17 | Expired |
| US6052776A | Branch operation system where instructions are queued until preparations is ascertained to be completed and branch distance is considered as an execution condition | Physics | 17 | Expired |
| US6078983A | Multiprocessor system having distinct data bus and address bus arbiters | Physics | 16 | Expired |
| US5148532A | Pipeline processor with prefetch circuit | Physics | 16 | Expired |
| US5206945A | Single-chip pipeline processor for fetching/flushing instruction/data caches in response to first/second hit/mishit signal respectively detected in corresponding to their logical addresses | Physics | 14 | Expired |
| US5881078A | Logic circuit having error detection function and processor including the logic circuit | Physics | 13 | Expired |
| US5878254A | Instruction branching method and a processor | Physics | 13 | Expired |
| US6333645A | Clocked logic gate circuit | Electricity | 12 | Expired |
| US4894799A | Content-addressable memory | Physics | 12 | Expired |
| US4942521A | Microprocessor with a cache memory in which validity flags for first and second data areas are simultaneously readable | Physics | 11 | Expired |
| US5790845A | System with reservation instruction execution to store branch target address for use upon reaching the branch point | Physics | 10 | Expired |
| US6316961A | Clocked logic gate circuit | Electricity | 4 | Expired |
| US5654651A | CMOS static logic circuit | Electricity | 3 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.