GaAs SCFL RAM
US4845681A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 1987 |
| Grant date | Jul 4, 1989 |
| Priority date | — |
| Expiry date | Oct 2, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A GaAs SCFL RAM having a unique three-voltage-level write circuit, direct-read circuitry with only one gate delay, diode-coupled FET logic cells, and peripheral circuitry with SCFL gates. The memory module architecture and plan of the RAM allow for several design options which may include 1K.times.16 and 16K.times.1 memory configurations. The RAM incorporates strobe circuitry for powering down selected memory modules, without loss of data, thus reducing power dissipation. The SCFL circuitry of the RAM functions with closely matched complementary signals for fast switching with minimum current spiking. The RAM has a wide range of threshold voltage tolerance, excellent noise margin, and a very high level of radioactive radiation hardness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.