James D. Joseph
17Patents
10h-index
15Co-inventors
69Inventor score
Filing activity: Jul 20, 1979 → Dec 17, 2008
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5802560A | Multibus cached memory system | Physics | 107 | Expired |
| US6049487A | Embedded static random access memory for field programmable gate array | Physics | 75 | Expired |
| US4468727A | Integrated cellular array parallel processor | Physics | 69 | Expired |
| US5875451A | Computer hybrid memory including DRAM and EDRAM memory components, with secondary cache in EDRAM for DRAM | Physics | 51 | Expired |
| US6718477B1 | Delay locked loop for an FPGA architecture | Physics | 26 | Expired |
| US4553260A | Means and method of processing optical image edge data | Physics | 25 | Expired |
| US5983313A | EDRAM having a dynamically-sized cache memory and associated method | Physics | 22 | Expired |
| US4465940A | Electro-optical target detection | Physics | 18 | Expired |
| US5566318A | Circuit with a single address register that augments a memory controller by enabling cache reads and page-mode writes | Physics | 14 | Expired |
| US4845681A | GaAs SCFL RAM | Physics | 11 | Expired |
| US4250376A | Apparatus for range finding equipment | Physics | 8 | Expired |
| US6976185B1 | Delay locked loop for an FPGA architecture | Physics | 6 | Expired |
| US7171575B1 | Delay locked loop for and FPGA architecture | Physics | 6 | Expired |
| US4754259A | Angle digitizer with enhanced harmonic rejection | Electricity | 4 | Expired |
| US7484113B1 | Delay locked loop for an FPGA architecture | Physics | 4 | Active |
| US5835442A | EDRAM with integrated generation and control of write enable and column latch signals and method for making same | Physics | 3 | Expired |
| US7941685B2 | Delay locked loop for an FPGA architecture | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.