Fabrication process for EEPROMS with high voltage transistors
US4851361A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 1988 |
| Grant date | Jul 25, 1989 |
| Priority date | — |
| Expiry date | Feb 4, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A CMOS fabrication process for EEPROMs having high-breakdown-voltage peripheral transistors in which a single implant step early in the process forms buried implants for both the memory cell's tunnel area source and the high voltage transistor's source and drain areas. The single implant step can be formed either before or after the formation of the channel stops and field oxide around the devices. The floating gate of the memory cell and the gates of the other devices are formed with polysilicon, the gates of the high voltage transistor overlapping the buried implants of its source and drain. The sources and drains of the other peripheral devices are then formed, using their polysilicon gates as a self-aligning mask. This may also include the formation of contact source and drain for the high voltage transistor. The process concludes with the formation of one or two layers of conductive lines connecting to specified drains, sources and gates to form a desired circuit pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.