Programmable variable-cycle clock circuit for skew-tolerant array processor architecture
US4851995A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 1987 |
| Grant date | Jul 25, 1989 |
| Priority date | — |
| Expiry date | Jun 19, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Using a variable-duration clock circuit, together with programmable duration control to alter the clock waveform within strict rules, permits the programmer to arrange appropriately short durations for short data transfers, and to arrange appropriately longer durations for longer data transfers in an array processor of myriad processing elements. There is no need to allow sufficient time in every clock cycle for worst case data transfer between remote processing elements. The clock waveform has three recognizable edges (A,B,C) regardless of loss of sharpness during its travel to the various processing elements. The convention that three skew-sensitive activities, READ, WRITE and OPERAND SUPPLY conform to respectively assigned edges as follows: PA0 A=READ; PA0 B=OPERAND SUPPLY; PA0 C=WRITE (Read next) The processing elements synchronize with the clock waveform, which is optimized for the instructions of the program being executed. There is no time wasted allowing for worst case data transfers possible in certain instructions but not possible in other instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.