Yarsun Hsu
11Patents
8h-index
10Co-inventors
69Inventor score
Filing activity: Jun 19, 1987 → Mar 13, 2008
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5822763A | Cache coherence protocol for reducing the effects of false sharing in non-bus-based shared-memory multiprocessors | Physics | 52 | Expired |
| US6094709A | Cache coherence for lazy entry consistency in lockup-free caches | Physics | 50 | Expired |
| US4851995A | Programmable variable-cycle clock circuit for skew-tolerant array processor architecture | Physics | 26 | Expired |
| US5287491A | Network rearrangement method and system | Electricity | 20 | Expired |
| US5778437A | Invalidation bus optimization for multiprocessors using directory-based cache coherence protocols in which an address of a line to be modified is placed on the invalidation bus simultaneously with sending a modify request to the directory | Physics | 20 | Expired |
| US5046000A | Single-FIFO high speed combining switch | Physics | 14 | Expired |
| US5313649A | Switch queue structure for one-network parallel processor systems | Electricity | 12 | Expired |
| US6175899A | Method for providing virtual atomicity in multi processor environment having access to multilevel caches | Physics | 12 | Expired |
| US6148375A | Hierarchical bus simple COMA architecture for shared memory multiprocessors having a bus directly interconnecting caches between nodes | Physics | 6 | Expired |
| US8108762B2 | Operating method and circuit for low density parity check (LDPC) decoder | Electricity | 5 | Active |
| US7719442B2 | Multi-mode multi-parallelism data exchange method and device thereof | Electricity | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.