Process for fabricating self-aligned silicide lightly doped drain MOS devices
US4855247A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1988 |
| Grant date | Aug 8, 1989 |
| Priority date | — |
| Expiry date | Dec 29, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/90
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method for fabricating an MOS structure, in accordance with one embodiment, a layer of material that serves as an etching stop during the side wall spacer etch, is inserted between the silicon substrate and the side wall spacer. In another embodiment of the invention, after establishing differential layer thicknesses on the source/drain surface, the side wall spacer is completely removed and light and heavy ion implantation steps are performed sequentially with one single lithographic step. In a further embodiment of the invention, after the self-aligned silicide is formed, the side wall spacer is removed, and light and heavy ion implantation steps are sequentially performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.