Output buffer with improved ESD protection
US4855620A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 1987 |
| Grant date | Aug 8, 1989 |
| Priority date | — |
| Expiry date | Nov 18, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output buffer having improved ESD tolerance is disclosed. The output buffer according to the invention incorporates a field oxide, or other high threshold voltage transistor, having its source-to-drain path connected between ground and the gate of the pull-down transistor, and has its gate connected to the output terminal. The threshold voltage of the high threshold device is greater than the power supply voltage, so as not to turn on during normal operation, but is lower than the BV.sub.CBO of the parasitic bipolar transistor associated with the pull-down transistor. The high threshold voltage device turns on with a positive voltage above its threshold appearing at the output terminal, such as occurs in an ESD event, resulting in the gate of the pull-down transistor being biased to ground. This causes the bipolar conduction, and the associated localized J-E heating, to take place away from the surface of the semiconductor, and away from the metal or silicide layers which provide the source of material for melt filaments. A similar high threshold transistor may be provided for biasing the gate of a pull-up transistor to the power supply terminal, having the same effect in the ev…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.