Patent · US Expired

Multi-stage, integrated decoder device having redundancy test enable

US4855621A · kind A · utility

10Cited by

10References

6Claims

0Family size

Assignee

Siemens Aktiengesellschaft · DE

Inventors

Kurt Hoffmann · Taufkirchen, DE
Rainer Kraus · Hersbruck, DE
Oskar Kowarik · Grafing, DE

Key dates

Filing date	Mar 16, 1988
Grant date	Aug 8, 1989
Priority date	—
Expiry date	Mar 16, 2008

Classification

Technology area (CPC G)Physics
CPC primaryG11C8/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A multi-stage, integrated decoder device includes a special function which facilitates the simultaneous activation of a plurality or as many as all of its outputs while gating out a pre-selectible output. When used as bit line decoder, it is thus possible to activate a plurality or up all of the bit lines (including any redundancy bit lines) of a block of storage cells of a semiconductor memory, excluding a bit line assumed to contain at least one defective storage cell.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.