Comparator array logic
US4857882A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 1988 |
| Grant date | Aug 15, 1989 |
| Priority date | — |
| Expiry date | Sep 14, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/0307
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A comparator array logic (CAL) circuit has a plurality of interconnected comparators arranged in an array. Each of the comparators stores a digital value. The CAL circuit stores all of the digital values in a monotonically increasing or decreasing order. Each of the comparators receives the input data signal and compares the input data signal to the digital value stored in the comparator. A comparison signal is generated in response to the comparison. The comparison signal from each comparator is received by an end cell which also receives the comparison signal from the immediately adjacent comparator. The end cell generates an output signal. An end cell is associated with each comparator. The plurality of output signals from the end cells represent the location of the comparator which borders the value of the input data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.