Graded extended drain concept for reduced hot electron effect
US4859620A · kind A · utility
24Cited by
7References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 20, 1988 |
| Grant date | Aug 22, 1989 |
| Priority date | — |
| Expiry date | May 20, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/965
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Hot electron injection into the gate oxides of MOSFET devices imposes limitations on the miniaturization of such devices in VLSI circuits. A buried channel with a graded, buried spacer is provided to guard against hot electron trapping effects while preserving process and structure compatibility with micron or submicron VLSI devices. The channel current is redirected into a buried channel at a distance away from the interface in the vicinity of the drain region where the hot electron effect is most likely to occur.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.