Ashing process of a resist layer formed on a substrate under fabrication to a semiconductor device
US4861424A · kind A · utility
30Cited by
3References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 19, 1988 |
| Grant date | Aug 29, 1989 |
| Priority date | — |
| Expiry date | Aug 19, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/427
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for removing a resist layer, in which high doses of ions have been implanted, by etching in a first step and a second step performed sequentially. In the first step, a carbonized region produced in the resist layer due to the high dose ion implantation is etched by applying plasma using hydrogen as a reactive gas at a temperature lower than a softening point of the resist layer. In the second step, a lower region, left after firstly etching the upper region, of the resist layer is etched by a conventional method such as a downstream ashing method or a wet stripping method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.