Process for making a high density split gate nonvolatile memory cell
US4861730A · kind A · utility
44Cited by
13References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 25, 1988 |
| Grant date | Aug 29, 1989 |
| Priority date | — |
| Expiry date | Jan 25, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/102
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A process is disclosed for producing a high density split gate nonvolatile memory cell which includes a floating gate and a control gate that is formed above the floating gate. The drain region is self-aligned to the floating gate and the source region is self-aligned to the control gate. Fully self-aligned implantation is made possible by the process and structure using self-aligned etch. Programming of the memory cell uses standard EPROM programming, and erasing is accomplished by Fowler-Nordheim tunneling or photoemission. The memory cell can be made with a reduced cell size and read current uniformity is obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.