High speed circuit testing apparatus having plural test conditions
US4862071A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 1988 |
| Grant date | Aug 29, 1989 |
| Priority date | — |
| Expiry date | Nov 18, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31937
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Supplied with an output response signal from a circuit under test in each test channel, a level comparator compares the signal with a reference level which defines a normal logical level. The compared output is applied to two independent signal detectors, wherein it is detected and held at the timing of two strobe pulses which are provided thereto via two different signal lines at a desired time interval. These detected signals are applied to two logical comparators, wherein they are compared with expected value signals, respectively. An expected value signal switching circuit may be provided by which the expected value signal in this test channel and the expected value signal in another test channel are selectively provided to one of the logical comparators. It is also possible to adopt an arrangement in which test results read out of a plurality of storage areas of a failure analysis memory are provided as mask data to a desired one of the logical comparators to thereby mask its logical comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.