Index for a register file with update of addresses using simultaneously received current, change, test, and reload addresses
US4862346A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 1985 |
| Grant date | Aug 29, 1989 |
| Priority date | — |
| Expiry date | Jul 2, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/0307
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital processor has four components: a controller, a data converter, a data register, and a logarithmic calculator. The processor has an address bus and a data bus for communication therewith. The address bus is connected to the controller. The data bus is connected to the controller and to the data register. Program instructions from the data bus are supplied to the controller and data on the data bus are supplied to the data register. Program instructions supplied to the controller are decoded and internal program instructions are generated by the controller. The controller communicates with the data converter, data register, and the logarithmic calculator via an internal bus through the internal program instructions. Integer data from the data bus are stored in the data register. The data converter receives the integer data, converts it into logarithmic data, and stores it in the data register. The logarithmic calculator receives the logarithmic data from the data register, operates it thereon, and supplies the resultant logarithmic calculation to the data register for storage. The data converter also communicates with the data register, receives the logarithmic data therefr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.