Two-transistor dram cell with high alpha particle immunity
US4864374A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 30, 1987 |
| Grant date | Sep 5, 1989 |
| Priority date | — |
| Expiry date | Nov 30, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM cell (8) having a storage node (18), a pass transistor (76) and a polysilicon word line (84) formed within an oxide isolated trench (68), thereby providing high soft error immunity. A write bit line (66) functions as the drain region (78) of the pass transistor (76) and is isolated from the substrate by a oxide isolation (64), thereby enhancing soft error immunity. The trench (68) includes an annular opening for providing intimate contact between the past transistor conduction channel (82) and the single crystal silicon substrate (36). During processing, the polysilicon conduction channel (82) of the pass transistor (76) is converted into single crystal silicon, thereby providing enhanced performance of the cell (8).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.