Image correlation system
US4864629A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 17, 1987 |
| Grant date | Sep 5, 1989 |
| Priority date | — |
| Expiry date | Dec 17, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06V10/7515
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for controlling a parallel combination of correlation circuits which compare image pixels. A number of correlation circuits are provided, each having its own memory. The memories are loaded with image data with each memory being assigned a different block (region) of the image. Each memory is also loaded with an overlapping portion of an adjacent block so that a pattern can be stepped across the entire block, including a match of the first column of the pattern with the last column of the block. The loading is done by generating addresses corresponding to addresses for the source image with one or more of the most significant bits modified so that the address sequence received by the second and subsequent memories are identical to the address sequence received by the first memory. This allows the various blocks of the image in the different memories to be later simulataneously accessed in parallel using a single address sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.