Testing arrangement for a DRAM with redundancy
US4866676A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 1988 |
| Grant date | Sep 12, 1989 |
| Priority date | — |
| Expiry date | Mar 24, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read/write memory has bit line pairs variously having a first or a second true/complement orientation. Data is selectively coupled to and from the bit line pairs to and from a data line pair via a column decoder. The memory has redundant bit line pairs aligned in the first true/complement arrangement. When a redundant bit line pair is implemented, the logic state of the data is inverted both for reading and for writing if the replaced bit line pair is of the second true/complement orientation. This results in the voltage impressed onto the memory cell for a given logic state is the same for the redundant bit line pair as for the bit line pair that it replaced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.