Inventor · Hornitos, CA, US

Richard Dewitt Crisp

108Patents
29h-index
38Co-inventors
90Inventor score

Filing activity: May 16, 1980 → Jun 9, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US6266730A High-frequency bus system Electricity 114 Expired
US6067594A High frequency bus system Electricity 85 Expired
US8670261B2 Stub minimization using duplicate sets of signal terminals Electricity 72 Active
US5680361A Method and apparatus for writing to memory components Physics 67 Expired
US8513817B2 Memory module in a package Electricity 60 Active
US8345441B1 Stub minimization for multi-die wirebond assemblies with parallel windows Electricity 58 Active
US5844855A Method and apparatus for writing to memory components Physics 57 Expired
US8254155B1 Stub minimization for multi-die wirebond assemblies with orthogonal windows Electricity 55 Active
US8338963B2 Multiple die face-down stacking for two or more die Electricity 49 Active
US4866676A Testing arrangement for a DRAM with redundancy Physics 49 Expired
US8441111B2 Stub minimization for multi-die wirebond assemblies with parallel windows Electricity 47 Active
US8436477B2 Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate Electricity 47 Active
US8502390B2 De-skewed multi-die packages Electricity 43 Active
US8436457B2 Stub minimization for multi-die wirebond assemblies with parallel windows Electricity 42 Active
US4488256A Memory management unit having means for detecting and preventing mapping conflicts Physics 39 Expired
US8659141B2 Stub minimization using duplicate sets of terminals for wirebond assemblies without windows Electricity 37 Active
US8513813B2 Stub minimization using duplicate sets of terminals for wirebond assemblies without windows Electricity 36 Active
US8405207B1 Stub minimization for wirebond assemblies without windows Emerging Cross-Sectional Technologies 35 Active
US8278764B1 Stub minimization for multi-die wirebond assemblies with orthogonal windows Electricity 34 Active
US8610260B2 Stub minimization for assemblies without wirebonds to package substrate Electricity 34 Active
US8525327B2 Stub minimization for assemblies without wirebonds to package substrate Electricity 33 Active
US5043943A Cache memory with a parity write control circuit Physics 33 Expired
US8823165B2 Memory module in a package Electricity 32 Active
US8659139B2 Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate Electricity 32 Active
US8659143B2 Stub minimization for wirebond assemblies without windows Emerging Cross-Sectional Technologies 32 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.