Single transistor electrically programmable memory device and method
US4868619A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 1986 |
| Grant date | Sep 19, 1989 |
| Priority date | — |
| Expiry date | Aug 14, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrically erasable programmable memory device which is programmable in the manner of an EPROM and erasable in the manner of an EEPROM. A dielectric layer between the control gate and the floating gate is provided having a high dielectric constant. A thin, uniform gate dielectric layer is provided which demonstrates minimal trapping. Finally, an asymmetrical source/drain junction is provided wherein the source includes a shallow portion and a deeper portion, which deeper portion defines the overlap between the source and the floating gate. In the preferred embodiment the dielectric between the control gate and the floating gate comprises tantalum pentoxide, the thin dielectric layer comprises oxynitride, and the deep diffusion portion of the source comprises phosphorous.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.