Non-volatile memory cell having Si rich silicon nitride charge trapping layer
US4870470A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 1987 |
| Grant date | Sep 26, 1989 |
| Priority date | — |
| Expiry date | Oct 16, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/69
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile storage cell comprising a field effect transistor having source, gate, and drain electrodes. The gate electrode includes a gate stack having a dielectric layer, a charge storage structure comprising a layer of silicon-rich silicon nitride having sufficient excess silicon to provide appreciable charge storage enhancement, without providing appreciable charge conductance enhancement, as compared to stoichiometric silicon nitride, and a charge injection means. A control electrode is disposed on the gate stack for effecting charge transfer to and from the silicon-rich silicon nitride layer through the charge injection means. An array of these cells is formed by disposing the FETs within independently biased substrate portions. Thus the cells can be overwritten without an intervening erasure cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.