DRAM controller cache
US4870622A · kind A · utility
102Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 24, 1988 |
| Grant date | Sep 26, 1989 |
| Priority date | — |
| Expiry date | Jun 24, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of minimizing memory access time on a memory with multiplexed address inputs between data stored in locations in memory in the same row but in different columns. First data is accessed at a predetermined column and row location. The predetermined row location of the first data is then recorded. The location of second data is then recorded. Then the locations of the first and second data are compared. A row compare signal is generated if the row value of both first and second data are identical. Only the column address is varied in response to the row compare signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.