Input protection device for C-MOS device
US4872045A · kind A · utility
1Cited by
1References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1983 |
| Grant date | Oct 3, 1989 |
| Priority date | — |
| Expiry date | Sep 2, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/611
Abstract
An input protection device for a C-MOS device having an n-type semiconductor substrate and a p-type well region. The device comprises a diode consisting of the p-type well region and an n.sup.+ -type layer diffusion formed in the p-type well region and connected between a gate of a C-MOS FET and ground. The n.sup.+ -type layer of the diode has a higher impurity concentration and a greater diffusion depth than those of n.sup.+ -type layers formed in the p-type well region and constitute the source and drain of an n-channel MOSFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.