Hierarchical scan selection
US4872169A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 8, 1988 |
| Grant date | Oct 3, 1989 |
| Priority date | — |
| Expiry date | Dec 8, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318558
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of testing circuitry is by the application of scan design which consists of a series of shift registers or latches which form a serial scan path through a logic circuit. The scan path can be used to observe and control logic elements in the design via serial scan operations. The present invention allows a continuous scan path to be compressed or expanded so that the scan path only passes through the desired logic element(s) to be tested. Devices connected on the serial scan path (or ring) can be selected or deselected thus allowing the serial path to either flow through or bypass a given logic circuit's internal scan path. The invention can be used to create a hierarchical scan network consisting of a primary scan ring from which a multiplicity of scan sub-rings may be accessed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.