Lee D. Whetsel
865Patents
35h-index
9Co-inventors
83Inventor score
Filing activity: Nov 5, 1987 → Aug 9, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5483518A | Addressable shadow port and protocol for serial bus networks | Physics | 132 | Expired |
| US6073254A | Selectively accessing test access ports in a multiple test access port environment | Physics | 107 | Expired |
| US4872169A | Hierarchical scan selection | Physics | 105 | Expired |
| US5056093A | System scan path architecture | Physics | 99 | Expired |
| US6408413B1 | Hierarchical access of test access ports in embedded core integrated circuits | Physics | 94 | Expired |
| US6643810B2 | Integrated circuits carrying intellectual property cores and test ports | Physics | 92 | Expired |
| US5084874A | Enhanced test circuit | Physics | 80 | Expired |
| US6199182A | Probeless testing of pad buffers on wafer | Physics | 79 | Expired |
| US5054024A | System scan path architecture with remote bus controller | Physics | 75 | Expired |
| US6763488B2 | Generator/compactor scan circuit low power adapter with counter | Physics | 68 | Expired |
| US5056094A | Delay fault testing method and apparatus | Physics | 66 | Expired |
| US5526365A | Method and apparatus for streamlined testing of electrical circuits | Physics | 61 | Expired |
| US6324662A | TAP and linking module for scan access of multiple cores with IEEE 1149.1 test access ports | Physics | 60 | Expired |
| US5103450A | Event qualified testing protocols for integrated circuits | Physics | 59 | Expired |
| US6499070B1 | Circuitry and method of transferring parallel and serial data | Electricity | 58 | Expired |
| US6378093B1 | Controller for scan distributor and controller architecture | Physics | 57 | Expired |
| US6046600A | Process of testing integrated circuit dies on a wafer | Physics | 57 | Expired |
| US7571364B2 | Selectable JTAG or trace access with data store and output | Physics | 54 | Active |
| US5606566A | Method and apparatus for streamlined concurrent testing of electrical circuits | Physics | 51 | Expired |
| US6242269A | Parallel scan distributors and collectors and process of testing integrated circuits | Physics | 48 | Expired |
| US6804725B1 | IC with state machine controlled linking module | Physics | 47 | Expired |
| US5495487A | Testing buffer/register | Physics | 45 | Expired |
| US5610826A | Analog signal monitor circuit and method | Physics | 45 | Expired |
| US5001713A | Event qualified testing architecture for integrated circuits | Physics | 45 | Expired |
| US5640521A | Addressable shadow port and protocol with remote I/O, contol and interrupt ports | Physics | 45 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.