Method of manufacturing a multichip package with increased adhesive strength
US4874721A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 1988 |
| Grant date | Oct 17, 1989 |
| Priority date | — |
| Expiry date | Oct 18, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49156
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a multichip package including the steps of forming a first polyimide insulating layer on a surface of a ceramic multilayer substrate having a circuit wiring therein, forming a first wiring connected to the circuit wiring of the multilayer substrate with a part of the first wiring being exposed at an open surface of the first polyimide insulating layer, forming a second polyimide insulating layer on a surface of a semiconductor element, and forming a second wiring connected with a circuit wiring of the semiconductor element in the second polyimide insulating layer with a part of the second wiring being exposed at an open surface of the second polyimide insulating layer. The method also includes positioning the semiconductor element on the substrate such that the part of the first wiring and the part of the second wiring oppose each other, and applying a predetermined pressure and a predetermined temperature in a predetermined gas atmosphere for a predetermined time period to cause the first and second polyimide layers to be cured and bonded with each other and to cause the parts of first and second wirings to be adhered to each other by thermal bonding.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.