Method of operating data buffer apparatus
US4875196A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 1987 |
| Grant date | Oct 17, 1989 |
| Priority date | — |
| Expiry date | Sep 8, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved First-In, First-Out data buffer and method of operation incorporates a plurality of arrays of random-access memory cells in column and row orientation per array in which all the cells in a row of one array are precharged simultaneously as memory cells are accessed for read or write operations in another array. Also, all the cells in a row of the other array may be precharged as the memory cells in the one array are accessed independently for read or write operations. Accesses to memory cells in addressed rows alternate from one array to another so that the signal conditioning of the memory cells in one array can take place before access in needed and while memory cells are being accessed in another array. Improved status logic unambigously designates the conditions of empty, half full and full, independent of the sequence of data read and write operations. Data signal driver circuitry controls the rate of change of data output signals for improved noise performance and compatibility with external circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.