Process for fabricating complimentary semiconductor devices having pedestal structures
US4876212A · kind A · utility
22Cited by
12References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 1, 1987 |
| Grant date | Oct 24, 1989 |
| Priority date | — |
| Expiry date | Oct 1, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating complimentary semiconductor devices having pedestal structures wherein both PNP and NPN transistors are formed simultaneously on the same substrate. After polysilicon layers have been patterned and etched, various polysilicon regions are doped with a plurality of conductivity types. This allows for there to be both P+ and N+ regions in the same polysilicon layer thereby enabling complimentary PNP and NPN transistors to be formed using a limited number of processing steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.