Integrated trench-transistor structure and fabrication process

US4881105A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Bijan Davari · Mahopac, US
• Wei Hwang · Armonk, US
• Nicky C. Lu · Yorktown Heights, US

Key dates

• Filing date: Jun 13, 1988
• Grant date: Nov 14, 1989
• Expiry date: Jun 13, 2008

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/513

Abstract

An integrated, self-aligned trench-transistor structure including trench CMOS devices and vertical "strapping transistors" wherein the shallow trench transistors and the strapping trench-transistors are built on top of buried source junctions. A p- epitaxial layer is grown on a substrate and contains an n-well, an n+ source and a p+ source regions. Shallow trenches are disposed in the epitaxial layer and contain n+ polysilicon or metal, such as tungsten, to provide the trench CMOS gates. A gate contact region connects the trenches and the n+ polysilicon or metal in the trenches. The n+ polysilicon or metal in the trenches are isolated by a thin layer of silicon dioxide on the trench walls of the gates. The p+ drain region, along with the filled trench gate element and the p+ source region, form a vertical p-channel (PMOS) trench-transistor. The n+ drain region, along with filled trench gate element and the n+ source form a vertical n-channel (NMOS) transistor. The PMOS and NMOS trench transistors are isolated by shallow trench isolation regions and an oxide layer.